Increased device density, together with higher speed performance and lower power consumption are major driving forces in efforts to improve IC devices and IC manufacturing methods. For example, CMOS design considerations for high speed digital applications are usually determined by the pull up time and pull down time for each individual gate. Gates have an associated delay time period for signal propagation. The delay time period, in turn, is inversely proportional to the drive current (Idrive). Maximizing the drive current increases the speed of a CMOS device.
Mechanical stresses are known to play a role in charge carrier mobility which affect several device parameters including Voltage threshold (VT) shift, drive current saturation (IDsat), and drive current (Idrive). Of particular importance as a measure of the speed of device performance is the value of Ion-Ioff (also referred to as (Idrive)). An increase in charge carrier mobility in the channel region of the MOS device will generally increase the drive current (Idrive).
One process for introducing mechanical strain into the channel region of the device is by implanting suitable species then annealing since the strain inducing species must be introduced substitutionally into the substrate lattice to generally be effective. Interstitial sites in the lattice are generally not effective in providing strain, and can instead result in increased defectivity. Species having a size larger than the size of the substrate atoms provide compressive strain and species smaller than the substrate atoms provide tensile strain. Such implant processes are generally performed at room temperature, and the associated annealing process is typically a relatively long processing time, such as on the order of several minutes, or more. Known strain implant/anneal approaches in general suffer from high manufacturing cost, process integration issues and difficulty in producing acceptable device quality due to high levels of residual end-of-range disorder in the completed devices.
As known in the art, end-of-range disorder refers to dislocation loops that are located beyond the amorphization region created by the implant that generally result in residual defects in the final IC that can reduce yield, device performance and in some cases device reliability. Conventional strain implant/anneal processes generally result in defect density of ≧1013 dislocation lines/cm2 primarily resulting from residual end of range disorder generated defects. These and other shortcomings demonstrate a continuing need in MOS device manufacturing for new strained channel MOS devices and manufacturing methods to reliably and predictably achieve significantly improved device performance while ensuring high yield and device reliability.